During the process flow of making state of the art DRAMs, a thin capacitor dielectric consisting of silicon dioxide and silicon nitride is typically formed. After patterning the polycrystalline silicon (polysilicon) plate of the planar capacitor, the remaining regions of the capacitor dielectric are stripped off. The polysilicon plate is then covered by an insulating or dielectric layer and the transistor gate dielectric, such as silicon dioxide, is grown. The present problems in current methods concern removing the capacitor dielectric and any nitrogen that may have diffused to the silicon surface, without damaging the monocrystalline silicon. If any nitrogen is left in the silicon, or if the silicon is damaged by the etch in the effort to remove the capacitor dielectric, then the gate dielectric, e.g. silicon dioxide, will be degraded and the performance of the adjacent transistor will be compromised.
Another difficulty with forming FETs adjacent capacitors concerns overetching. Typically, the top plate of a planar MOS capacitor is doped polysilicon. The etch of this polysilicon layer traditionally has been stopped at the thin dielectric layer of the capacitor underlying the polysilicon layer, but because the dielectric layer is so thin, often the process would etch through both the dielectric layer and part of the underlying silicon substrate, damaging the future FET fabrication area. Ideally, an improved fabrication process would avoid this problem.
The use of capacitors adjacent a transistor forms a one-transistor memory storage cell for a dynamic random access memory (DRAM), a particular high-volume type of semiconductor memory. However, capacitors adjacent FETs also occur in many other types of semiconductor integrated circuits.
U.S. Pat. No. 4,466,177 to Chao discloses a prior art process for the fabrication of capacitors adjacent to transistors where the capacitor dielectric and the transistor gate dielectric layers are separately grown. It is noted that the method of U.S. Pat. No. 4,466,177 is applicable only to single polysilicon processes only. Further, the substrate in the 4,466,177 process is also undesirably exposed to etching, handling and cleaning effects. Another of the problems with using the method of U.S. Pat. No. 4,466,177 to provide separately tailored dielectric layers for the capacitors and the FETs is that inadequate protection is provided to prevent nitrogen from diffusing to the silicon surface of the FET fabrication areas. It would be advantageous to discover a process by which the substrate surface was kept protected until just prior to forming the capacitor dielectric or the FET gate oxide.
One approach to solving the problem of a damaged substrate in the area where FETs are to be formed is to form, preferably by growing, a sacrificial oxide layer which is etched off just prior to the formation of the FET gate oxide.
Additionally, for background information, U.S. Pat. No. 4,603,059 teaches an alternate prior art method for making capacitors adjacent FETs where the capacitor dielectric is a three-ply dielectric layer of a first silicon oxide film, a nitride film, and a second oxide film.
Thus, it would be an advance in the integrated circuit fabrication art if a method were discovered for fabricating planar capacitors and FETs adjacent each other, wherein the capacitor dielectric may be etched without damaging the semiconductor substrate where the FET is to be formed. Preferably, such a method would also inhibit the diffusion of nitrogen into the FET fabrication area as well.